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Name:
Hardware Design of an Expandable High-speed Signal Process Evaluatin Module
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]Author:
GuoXiaoLiang
Tutor: LiangGuoLong
School:
Harbin Engineering University
Course: Underwater Acoustics
Keywords: NIOS Ⅱ,FPGA,μC/OS-Ⅱ,three switches,FFT
CLC: TN911.7
Type: Master's thesis
Year: 2012
Abstract:
With the increasingly complex and flexible digital signal processing technology,traditional hard-core and solid core embedded hardware platform can not meet the designrequirements. Performance can be customized, functions can be cut and resources can beextended to the portability of embedded hardware platform has become a hot research today.A portable embedded core board that FPGA as the core processing performance can becustomized, peripheral functions can be cut, expansion of resource allocation has beendesigned, and its functional verification has been done in this paper.In this paper, a core board has been designed which has an FPGA as processing chip,and FLASH, SDRAM, SRAM, EPCS as the memary area, and the necessary power circuitcomposed of a flexible FPGA minimum system. According to different applicationrequirements, it can be complete a variety of system-level design without changing thehardware design.This paper firstly introduced the core board involved in related technologies, and thencarried out a detailed analysis of the hardware design of the core board from the deviceselection to the design of each module. Based on the hardware platform, this paper alsocarried out this core board functional verification of design, including the SOPC Buidlercustom NIOS II-based on-chip programmable system, simulation test design calls for usingVerilog HDL design logic modules, preparation of the driver and the preparation of the UC/OS-II application for SOPC. In the above is completed, there is a entire functionalverification of design, simulation and testing, and finally by the FFT algorithm this paperalso gave an analyze of the performance of this core board.Functional verification showed that this core board for the performance of the FFTalgorithm that can achieve high speed, high-precisionmulti-channel digital signal processingfunctions.
With the increasingly complex and flexible digital signal processing technology,traditional hard-core and solid core embedded hardware platform can not meet the designrequirements. Performance can be customized, functions can be cut and resources can beextended to the portability of embedded hardware platform has become a hot research today.A portable embedded core board that FPGA as the core processing performance can becustomized, peripheral functions can be cut, expansion of resource allocation has beendesigned, and its functional verification has been done in this paper.In this paper, a core board has been designed which has an FPGA as processing chip,and FLASH, SDRAM, SRAM, EPCS as the memary area, and the necessary power circuitcomposed of a flexible FPGA minimum system. According to different applicationrequirements, it can be complete a variety of system-level design without changing thehardware design.This paper firstly introduced the core board involved in related technologies, and thencarried out a detailed analysis of the hardware design of the core board from the deviceselection to the design of each module. Based on the hardware platform, this paper alsocarried out this core board functional verification of design, including the SOPC Buidlercustom NIOS II-based on-chip programmable system, simulation test design calls for usingVerilog HDL design logic modules, preparation of the driver and the preparation of the UC/OS-II application for SOPC. In the above is completed, there is a entire functionalverification of design, simulation and testing, and finally by the FFT algorithm this paperalso gave an analyze of the performance of this core board.Functional verification showed that this core board for the performance of the FFTalgorithm that can achieve high speed, high-precisionmulti-channel digital signal processingfunctions.
Dissertation URL:http://www.topresearch.org/showinfo-246-681464-0.html
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