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Design of Data Delayer and Memorizer Based on FPGA

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Author
Tutor: SunJingJing; YuBenLi
School: Anhui University
Course: Optics
Keywords: the FPGA chip,RAM delayer,No change mode,Read First mode,SD card,FAT16file syste
CLC: TP333
Type: Master's thesis
Year:  2014
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Abstract:
FPGA device is a kind of programmable logic array, which is belongs to Semi-custom circuit in the field of Application Specific Integrated Circuit (ASIC). It solves the problem that the gate numbers of original programmable device are limited. This paper designs dual port RAM data delayer based on FPGA chip in the Read First mode. This data delayer solves the problem that two bus signals need delayed time in different period. At last we design SD card in the control of the FPGA chip to store demodulation data.The first chapter introduces the research background of this article and the FPGA development course and the structure features. This chapter gives the research purpose and meaning in this paper.The second chapter mainly introduces the design principle of FPGA chips with four aspects explained in FPGA design flow chart.The third chapter mainly introduces the design method of data delayer based on FPGA, and compares the Read First mode dual port RAM data delayer with the No Change mode dual port RAM data delayer in clock frequency and resource consumption.The fourth chapter mainly introduces the SD card storage system, and FAT16file system in SD card.At last we design each module and do simulation in each module.The fifth chapter gives a brief summary about this paper and the ideas of the future research work.
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